1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a column address decoder for a two bit prefetch and decoding method thereof.
2. Description of the Related Art
A semiconductor memory device includes a memory cell array for storing data. The memory cell array includes a plurality of memory cells connected to m word lines and n bit lines. The n bit lines are connected to input and output lines through n column selecting line gates. One of the m word lines and one of the n column selecting line gates are selected in order to read the data stored in the memory cell array. The data of the memory cell connected to the selected word line is loaded onto the bit lines. The data loaded onto the bit lines is loaded onto the input and output lines through the selected column selecting line gates. The data loaded onto the input and output lines is output to the outside through an input and output pad.
According to the conventional technology, one item of data is read from or written into the memory cell array by activating one column selecting line gate at a time. However, as the operating speed of a system using the semiconductor memory device (for example, a central processing unit CPU) becomes higher, it is required that the data processing speed of the semiconductor memory device is improved. Therefore, a method of increasing the amount of simultaneously transmitted data is used when data is written to the memory cell array or is read from the memory cell array in order to increase the operating speed of the semiconductor memory device. By increasing the amount of simultaneously transmitted data, the data processing speed of the semiconductor memory device can be increased.